Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit including a plurality of ADCs subjected to interleave-operation in parallel, or a semiconductor integrated circuit including an imaging ADC using a plurality of circuit elements to be switched sequentially, in which even when an image signal of any specification is input, an output signal of the plurality of ADCs or the imaging ADC is averaged to reduce irregularities on a screen. The semiconductor integrated circuit includes a plurality of analog/digital converting circuits ( 11 ) operated in parallel for sequentially converting an analog image signal to a digital image signal, a multi-phase clock signal generating circuit ( 12 ) for generating multi-phase clock signals to be used for periodically operating the plurality of analog/digital converting circuits ( 11 ) in a certain order, and a control circuit ( 20 ) for controlling the multi-phase clock signal generating circuit ( 12 ) to change a period or an order of operating the plurality of analog/digital converting circuits ( 11 ).

This application is a 371 of PCT/JP03/03240 filed Mar. 18, 2003.

TECHNICAL FIELD

The present invention relates generally to semiconductor integratedcircuits, and more particularly to a semiconductor integrated circuitincluding an imaging ADC (analog to digital converter) for converting ananalog image signal to a digital image signal.

BACKGROUND ART

In these years, the resolution of a digital image display device such asLCD (liquid crystal display) or PDP (plasma display panel) has beenimproved in recent years. The operating speed of an LSI (large scaleintegration) for converting an analog image signal to a digital imagesignal has correspondingly been increased. For operating an LSI at ahigh speed, the circuit is usually designed to use finer transistorshaving a smaller stray capacitance and a higher current driving force.With respect to a part of the LSI which cannot be easily made operate ata high-speed, a technique for operating a plurality of circuits havingthe identical function in parallel is employed to obtain substantialhigh-speed operation.

Even in an imaging ADC for supplying a digital image signal to a digitalimage display device, as in the above case, an advanced processingtechnology is used to widen a bandwidth, and the parallel operationbased on interleave operation is used. However, there are variations incharacteristics among a plurality of ADCs for performing paralleloperation due to the limitation of a micro-machining technology. Thisresults in deteriorated characteristics, for example, generation of adifferential linearity error or an integral linearity error.

FIG. 12 shows an exemplary configuration of a prior art imaging ADC. Theimaging ADC 110 has first to N-th ADCs 111 for performing paralleloperation, a multi-phase clock signal generating circuit 112 forsupplying multi-phase clock signals to the ADCs 111, and a selectorcircuit 113 for selecting one of output signals of the ADCs 111. Thefirst to N-th ADCs 111 sequentially convert an analog signal to adigital signal in synchronism with the multi-phase clock signalsreceived from the multi-phase clock signal generating circuit 112. Inthis example, reference symbol N denotes a degree of parallelism of theADCs.

In general, in an image signal, as shown in FIG. 13, pixel informationcorresponding to one line continues from the upper left of the screen tothe horizontal direction, and then under the line by one pixel in thevertical direction, pixel information corresponding to another line alsocontinues from the left side of the screen to the horizontal direction.The repetition of the above-mentioned pixel information forms an imagesignal corresponding to one frame. A number of pixels in one frame, thatis, a sampling number of times M in one frame can be obtained from aproduct of a number of pixels in one line and a number of lines in oneframe.

Assume that the sampling number of times M in one frame is divisible bythe degree N of parallelism of ADCs, and that the first ADC samples apixel P (I, 1), the second ADC samples a pixel P (I, 2), and the N-thADC samples a pixel P (I, N) in a frame (I). Then, even in a frame(I+1), the first ADC samples a pixel P (I+1, 1), the second ADC samplesa pixel P (I+1, 2), and the N-th ADC samples a pixel P (I+1, N), in asimilar manner. In this case, P (I, J) denotes a J-th pixel in an I-thframe. In such a case, if the first to N-th ADCs vary incharacteristics, even when an identical analog signal is inputted to theADCs, a constant pattern of error occurs in an output digital signal,which results in appearance of irregularities on the display screen.

For the purpose of suppressing the influences of variations in circuitelements including a resistor and a capacitor upon analog/digitalconversion characteristics during conversion from an analog image signalto a digital image signal by using a single ADC, output results of theADC are averaged by sequentially switching (swapping) between aplurality of circuit elements. Even in such a case, with respect topixels for a plurality of successive frames, if a plurality of circuitelements in the ADC are arranged in the same cycle or sequence,irregularities appear on the screen.

For the purpose of reducing irregularities on the screen caused by suchvariations, it is also considered to digitally correct the output signalof the imaging ADC. However, such digital correction requirescomplicated circuit and processing.

DISCLOSURE OF THE INVENTION

In view of the above respects, in a semiconductor integrated circuitincluding a plurality of parallel interleave-operating ADCs or animaging ADC for sequentially switching between a plurality of circuitelements, it is an object of the present invention to reduceirregularities on a display screen by averaging output signals of one ormore imaging ADC to reduce irregularities on a screen.

In order to resolve the above-mentioned object, a semiconductorintegrated circuit according to a first aspect of the present inventioncomprises a plurality of analog/digital converting circuits operated inparallel for sequentially converting an analog image signal to a digitalimage signal, a multi-phase clock signal generating circuit forgenerating multi-phase clock signals to be used for periodicallyoperating the plurality of analog/digital converting circuits in acertain order, and a control circuit for controlling the multi-phaseclock signal generating circuit to change at least one of a period andan order of operating the plurality of analog/digital convertingcircuits.

Further, a semiconductor integrated circuit according to a second aspectof the present invention comprises an analog/digital converting circuitfor converting an analog image signal to a digital image signal bysequentially switching between a plurality of circuit elements, a firstcontrol circuit for controlling the analog/digital converting circuit toperiodically arrange the plurality of circuit elements in a certainorder, and a second control circuit for controlling the first controlcircuit to change at least one of a period and an order of arranging theplurality of circuit elements.

According to the present invention arranged as mentioned above, in thecase where the plurality of analog/digital converting circuits areoperated in parallel, the period or order of operating theseanalog/digital converting circuits is changed. Also, in the case wherethe single analog/digital converting circuit is used by sequentiallyswitching between the plurality of circuit elements, the period or orderof arranging these circuit elements is changed. In this way, even whenan image signal of any specification is inputted, the output signal ofthe imaging ADC is averaged and irregularities on the screen can bereduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The advantages and features of the present invention will be moreclearly understood with respect to the detailed description anddrawings, in which constituent elements having the same functions aredenoted by the same reference numerals or symbols.

FIG. 1 is a block diagram showing a configuration of a semiconductorintegrated circuit according to a first embodiment of the presentinvention;

FIG. 2 is a timing chart showing waveforms of signals appearing atvarious points in an imaging ADC as shown in FIG. 1;

FIG. 3 is another timing chart showing waveforms of signals at variouspoints in the imaging ADC as shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a firstmodification of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

FIG. 5 is a timing chart showing waveforms of signals at various pointsin an imaging ADC as shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a secondmodification of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

FIG. 7 is a timing chart showing waveforms of signals at various pointsthe an imaging ADC as shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a semiconductorintegrated circuit according to a second embodiment of the presentinvention;

FIG. 9 is a timing chart showing waveforms of signals at various pointsin an imaging ADC as shown in FIG. 8;

FIG. 10 is a circuit diagram showing the principle of a semiconductorintegrated circuit according to a third embodiment of the presentinvention;

FIG. 11 is a block diagram showing a configuration of the semiconductorintegrated circuit according to the third embodiment of the presentinvention;

FIG. 12 is a block diagram showing a configuration of a prior artimaging ADC; and

FIG. 13 shows an array of pixels on frames.

BEST MODE FOR CARRYING OUT THE INVENTION

Firstly, there will be described a first embodiment of the presentinvention.

FIG. 1 is a block diagram showing a configuration of a semiconductorintegrated circuit according to a first embodiment of the presentinvention. As shown in FIG. 1, the semiconductor integrated circuitincludes an imaging ADC 10 and a sampling control signal generatingcircuit 20. The imaging ADC 10 has first to N-th ADCs 11 for performingparallel operation, a multi-phase clock signal generating circuit 12 forgenerating multi-phase clock signals to be used for operating these ADCs11 periodically in a certain order, and a selector circuit 13 forselecting one of output signals of the ADCs 11.

The sampling control signal generating circuit 20 outputs a samplingcontrol signal on the basis of a master clock signal. In the imaging ADC10, the multi-phase clock signal generating circuit 12 generates themulti-phase clock signals on the basis of the master clock signal andthe sampling control signal received from the sampling control signalgenerating circuit 20, and supplies the multi-phase clock signals to therespective ADCs 11. The first to N-th ADCs 11 converts an input analogsignal to a digital signal in synchronism with the multi-phase clocksignals generated by the multi-phase clock signal generating circuit 12,and outputs the converted digital signal. The selector circuit 13selects one of the digital signals outputted from the ADCs 11 inaccordance with the multi-phase clock signals, and then outputs theselected digital signal.

FIG. 2 is a timing chart showing waveforms of signals appearing atvarious points in the case where N=3 in the imaging ADC 10 shown inFIG. 1. On the basis of the master clock signal and the sampling controlsignal, the multi-phase clock signal generating circuit 12 generatesmulti-phase clock signals Φ1, Φ2 and Φ3 to be used for cyclicallyoperating the first, second and third ADCs.

Now assume that a sampling number of times in one frame is representedby M where M=(a number of pixels in one line)×(a number of lines in oneframe) and M is a multiple of 3. Then each of the ADCs samples the samepixel on the screen in a plurality of frames. As a result,irregularities corresponding to variations among the ADCs appear on thescreen. In the present embodiment, for the purpose of preventing theabove-mentioned irregularities appearance, the sampling timing of theADCs are shifted, for example, in a blanking period of an image signal.As a result, even when an image signal of any specification is input,irregularities on the screen can be reduced.

As shown in FIG. 1, the semiconductor integrated circuit according tothe present embodiment includes the sampling control signal generatingcircuit 20 for generating the sampling control signal to be used forshifting the sampling timing in a predetermined state. On the basis ofthe sampling control signal, the multi-phase clock signal generatingcircuit 12 shifts phases of the multi-phase clock signals to begenerated.

As shown in FIG. 2, when the sampling control signal is changed to itshigh level, the multi-phase clock signal generating circuit 12 shiftsthe phases of the multi-phase clock signals to be generated by an amountcorresponding to at least one pulse of a master clock signal CK. As aresult, the ADCs are operated at timing shifted by at least one pulse ofthe master clock signal CK, so as to prevent the same ADC from samplingthe same pixel on the screen in successive two frames.

FIG. 3 is a timing chart showing waveforms of signals appearing atvarious points when a sampling period is varied in the case where N=3 inthe imaging ADC 10 shown in FIG. 1. On the basis of the master clocksignal and the sampling control signal, the multi-phase clock signalgenerating circuit 12 generates multi-phase clock signals Φ1, Φ2 and Φ3to be used for cyclically operating the first, second and third ADCs.The period of cyclically operating the first, second and third ADCs iscontrolled by the sampling control signal.

When the period of cyclically operating the first, second and third ADCsis varied for every frame, all pixels are prevented from being sampledalways by the same ADC and irregularities on the screen are averaged ona time basis, which results in that the irregularities cannot bevisually recognized.

Hereinafter, there will be described a sampling control method used inthe present embodiment. It is assumed in the following explanation thata sampling number of times in one frame, that is, (the number of pixelsin one line)×(the number of lines in one frame) is denoted by M and thata degree of parallelism of ADCs, that is, the number of ADCs operated inparallel is denoted by N, where each of M and N is an integer equal toor larger than 2. It is also assumed that a remainder when M is dividedby N is denoted by K (K=M mod N).

A first sampling control method will be explained. In the case whereK=0, by obtaining such L satisfying a requirement that a remainder when(M+L) is divided by N is not zero, the sampling timing is shifted by anamount corresponding to L pulses of the master clock signal in oneframe. Accordingly, the same parallel-operating ADCs can be preventedfrom sampling pixels at the same positions at least in successive twoframes. As a result, when the number of parallel-operating ADCs is twoor more, the averaging effect by at least two ADCs can be obtained.

Next, there will be described a second sampling control method. In thecase where K=0 or in the case where K≠1 and N is divisible by K (N modK=0), by obtaining such L that N and J (J≠0) are mutually primes where Jrepresents a remainder when (M+L) is divided by N (J=(M+L) mod N), thesampling timing is shifted by an amount corresponding to L pulses of themaster clock signal in one frame. For example, when M=1688 and N=8, Lsatisfying this conditions is 1, 3, 5 or 7. In this manner, when thenumber of parallel-operating ADCs is N, the averaging effect by N ADCscan be achieved.

Next, there will be described a third sampling control method. Apseudorandom number generating circuit for generating an integer withina range from zero to (N−1) is prepared. When the pseudorandom numbergenerating circuit has an output L(i) for an i-th frame, the samplingtiming is shifted by an amount corresponding to L(i) pulses of themaster clock signal in this frame. When the pseudorandom numbergenerating circuit has an output L(i+1) for the next (i+1)-th frame, thesampling timing is shifted by an amount corresponding to L(i+1) pulsesof the master clock signal in the next frame.

In this manner, the sampling order of the parallel ADCs for sampling thesame pixel can be made non-uniform on a time base at least within theperiod of the pseudorandom numbers. Thus unlike the aforementioned firstand second sampling control methods, substantially non-uniform averagingeffect can be obtained.

Next, there will be described a first modification of the semiconductorintegrated circuit according to the present embodiment, by referring toFIGS. 4 and 5.

As shown in FIG. 4, the semiconductor integrated circuit includes animaging ADC 30 and a sampling control signal generating circuit 40. Theimaging ADC 30 has first to N-th ADCs 11, a multi-phase clock signalgenerating circuit 31 for generating multi-phase clock signals whichdefine sampling timing of these ADCs 11, and a selector circuit 13 forselecting one of output signals of the ADCs 11. The multi-phase clocksignal generating circuit 31, which has a counter 32 provided therein,generates multi-phase clock signals on the basis of the master clocksignal, a phase control number and a sampling control signal.

The sampling control signal generating circuit 40 generates the samplingcontrol signal on the basis of a control flag and a verticalsynchronization signal VSYNC. More specifically, when the control flagis set, the sampling control signal generating circuit 40 generates thesampling control signal by using a transition edge of the verticalsynchronization signal VSYNC as a reference, and supplies the samplingcontrol signal to the imaging ADC 30. In this connection, as well as thevertical synchronization signal VSYNC, a horizontal synchronizationsignal HSYNC or another signal synchronized with the verticalsynchronization signal VSYNC or with the horizontal synchronizationsignal HSYNC may be used.

In the imaging ADC 30, the counter 32 provided in the multi-phase clocksignal generating circuit 31 counts the master clock signal, and storesstates for generation of the multi-phase clock signals as countervalues. The counter 32, in response to the sampling control signal,changes its counter value by a number set as the phase control number.This causes the multi-phase clock signal generating circuit 31 to changethe phases of the multi-phase clock signals.

FIG. 5 is a timing chart showing waveforms of signals appearing atvarious points in the imaging ADC 30 shown in FIG. 4 in the case whereN=3. When the edge of the vertical synchronization signal VSYNC istransited while the control flag is set in a vertical blanking period orthe like, the sampling control signal generating circuit 40 changes thesampling control signal to its high level. In the imaging ADC 30, thecounter 32 in the multi-phase clock signal generating circuit 31 countsthe master clock signal CK, and when the sampling control signal ischanged to high level, the counter changes its counter value by a numberset as the phase control number. As a result, the phases of themulti-phase clock signals Φ1, Φ2 and Φ3 vary as shown in FIG. 5. In FIG.5, the phase control number is set at “1”.

In this example, a total sampling number of times is not changed, andtherefore, given a timing margin, sampling control can be possible evenin a period other than the blanking period.

Next, a second-modification of the semiconductor integrated circuitaccording to the present embodiment will be described by referring toFIGS. 6 and 7.

As shown in FIG. 6, the semiconductor integrated circuit includes animaging ADC 50 and a counter 60. The imaging ADC 50 hasparallel-operating first to N-th ADCs 11, a multi-phase clock signalgenerating circuit 51 for generating multi-phase clock signals to definethe sampling timing of these ADCs 11, and a selector circuit 13 forselecting one of output signals of the ADCs 11. The multi-phase clocksignal generating circuit 51, which has a counter 52 therein, generatesmulti-phase clock signals on the basis of a master clock signal, a phasecontrol number, and a sampling control signal.

The counter 60 generates the sampling control signal on the basis of themaster clock signal and a control flag. More specifically, when thecontrol flag is set, the counter 60 counts pulses of master clocksignals, generates the sampling control signal at intervals of apredetermined period, and supplies the sampling control signal to theimaging ADC 50.

In the imaging ADC 50, the counter 52 in the multi-phase clock signalgenerating circuit 51 counts the master clock signal and also storesstates for generation of the multi-phase clock signals as countervalues. The counter 52, in response to the sampling control signal,changes the counter values by a number set as the phase control number.This causes the multi-phase clock signal generating circuit 51 to changethe phases of the multi-phase clock signals.

FIG. 7 is a timing chart showing waveforms of signals appearing atvarious points in the imaging ADC 50 shown in FIG. 6 in the case whereN=3. When a control flag is set, the counter 60 counts pulses of themaster clock signal CK and changes the sampling control signal to itshigh level at intervals of a predetermined period. In the imaging ADC50, when the sampling control signal is changed to high level, thecounter 52 in the multi-phase clock signal generating circuit 51 changesits counter values by a number set as the phase control number. As aresult, the phases of the multi-phase clock signals Φ1, Φ2 and Φ3 varyas shown in FIG. 7. In FIG. 7, the phase control number is set at “1”.

Next, there will be described a second embodiment of the presentinvention.

FIG. 8 is a block diagram showing a configuration of a semiconductorintegrated circuit according to a second embodiment of the presentinvention. As shown in FIG. 8, the semiconductor integrated circuitincludes an imaging ADC 70 and a clock signal control circuit 80. Theimaging ADC 70 has a first to N-th ADCs 11 for performing paralleloperation, a multi-phase clock signal generating circuit 71 forgenerating multi-phase clock signals to periodically operate the ADCs 11in a certain order, and a selector circuit 13 for selecting one ofoutput signals of the ADCs 11.

On the basis of a master clock signal, a control flag, a phase controlnumber and a vertical synchronization signal VSYNC, the clock signalcontrol circuit 80 supplies a clock signal to the multi-phase clocksignal generating circuit 71. When the control flag is set, the clocksignal control circuit 80 generates from the master clock signal asignal whose pulses are suppressed by a number set as the phase controlnumber, by using the transition edge of the vertical synchronizationsignal VSYNC as a reference, and supplies the generated signal as theclock signal to the multi-phase clock signal generating circuit 71. Inthis connection, in place of the vertical synchronization signal VSYNC,a horizontal synchronization signal HSYNC or another signal synchronizedwith the vertical synchronization signal VSYNC or the horizontalsynchronization signal HSYNC may be used.

In the imaging ADC 70, on the basis of the clock signal received fromthe clock signal control circuit 80, the multi-phase clock signalgenerating circuit 71 generates multi-phase clock signals to be used forsequentially operating the first to N-th ADCs 11, and supplies thegenerated multi-phase clock signals to the ADCs 11.

FIG. 9 is a timing chart showing waveforms of signals appearing atvarious points in the imaging ADC 70 shown in FIG. 8 in the case whereN=3. When the control flag is set in the vertical blanking period, theclock signal control circuit 80 generates a signal having pulsesobtained by suppressing the pulses of the master clock signal CK by anumber set as the phase control number from the transition edge of thevertical synchronization signal VSYNC, and supplies the generated signalas the clock signal to the multi-phase clock signal generating circuit71 of the imaging ADC 70. When receiving the clock signal, themulti-phase clock signal generating circuit 71 generates multi-phaseclock signals Φ1, Φ2 and Φ3 to be used for cyclically operating thefirst, second, and third ADCs. In FIG. 9, the phase control number isset at “1”.

In this manner, irregularities on the screen can be reduced by theaveraging effect of the plurality of ADCs for performing paralleloperation. However, since a total sampling number is reduced, thisoperation is required to be carried out in a blanking period duringwhich this operation has no influence upon the screen.

The aforementioned technique is effective not only when a plurality ofADCs are used in parallel for interleave operation, but also when asingle ADC is used for converting an analog image signal to a digitalimage signal while the output signal of the ADC is averaged bysequentially switching (swapping) between a plurality of circuitelements in order to suppress the influences of variations in circuitelements such as a resistor and a capacitor that influence theanalog/digital conversion characteristics (including when a plurality ofcircuit elements form a circuit block). As the circuit block, anamplifier circuit such as a differential amplifier or an operationalamplifier can be used. In the case of such a circuit configuration thatAD conversion is carried out through a plurality of steps like in apipeline ADC, a sub-ADC or a sub-DAC corresponds to the circuit block.

Next, a third embodiment of the present invention using such ADC will beexplained. Now, consider the case where a power potential V_(DD) isdivided by resistors R1 and R2 whose resistance values are designed tobe equal to each other to generate a midpoint potential VM of the powerpotential V_(DD) as shown in FIG. 10. In this case, it is assumed that arelation R1=R2+ΔR is actually satisfied due to variations in the elementformation. When the resistors R1 and R2 are connected as shown in theleft side of FIG. 10, a midpoint potential VM1 is expressed by equation(1) as follows:

$\begin{matrix}{{VM1} = {{V_{DD}\frac{R2}{{R1} + {R2}}} = {V_{DD}\left( {\frac{1}{2} - \frac{\Delta\; R}{2\left( {{2{R2}} + {\Delta\; R}} \right)}} \right)}}} & (1)\end{matrix}$

While the positions of the resistors R1 and R2 are reversely connectedby switching between the resistors as shown in the right side of FIG.10, a midpoint potential VM2 is expressed by equation (2) as follows:

$\begin{matrix}{{VM2} = {{V_{DD}\frac{R1}{{R1} + {R2}}} = {V_{DD}\left( {\frac{1}{2} + \frac{\Delta\; R}{2\left( {{2{R2}} + {\Delta\; R}} \right)}} \right)}}} & (2)\end{matrix}$

Accordingly, when the two states are averaged by alternate switching,V_(DD)/2 can be accurately generated as the midpoint potential VM.

FIG. 11 is a block diagram showing a configuration of a semiconductorintegrated circuit according to a third embodiment of the presentinvention.

As shown in FIG. 11, the semiconductor integrated circuit includes animaging ADC 90 and a switching control signal generating circuit 100.The imaging ADC 90 converts an analog image signal to a digital imagesignal by sequentially switching between a plurality of circuitelements. FIG. 11 shows the imaging ADC including first to N-th elements91, and a switch 92 for switching these elements 91 to be connected tothe first to N-th node.

The imaging ADC 90 is provided therein with a multi-phase control signalgenerating circuit 93 which generates multi-phase control signals on thebasis of a master clock signal and a sampling control signal receivedfrom the switching control signal generating circuit 100. Themulti-phase control signals are used for controlling the ADC in such amanner that the first to N-th elements 91 are periodically arranged in acertain order.

In such an imaging ADC, the influences of variations among theseelements can be averaged because the switch 92 switches connectionsbetween the first to N-th elements 91 and first to N-th nodes. When sucha technique is used in the imaging ADC, however, combinations of theelements for performing AD conversion on the same pixel may become thesame for a plurality of frames due to the periodicity of the imagesignal. In such a case, the averaging effect cannot be obtained, andtherefore, irregularities appear on the screen. To avoid this, by usinga technique similar to that explained in the first and secondembodiments of the present invention to control the multi-phase controlsignal generating circuit 93, the influences of variations in theplurality of elements are averaged and irregularities on the screen arereduced even when the image signal of any specification is inputted.

To this end, the switching control signal generating circuit 100generates a switching control signal for controlling the multi-phasecontrol signal generating circuit 93 in such a manner that an ADCportion changes the period or an order of arranging the plurality ofcircuit elements. On the basis of the master clock signal and thesampling control signal received from the switching control signalgenerating circuit 100, the multi-phase control signal generatingcircuit 93 changes the phases of the multi-phase control signals. Theswitch 92 changes connections between the first to N-th elements 91 andthe first to N-th ADCs nodes according to the multi-phase controlsignals. As a result, variations in the first to N-th elements 91 can berandomly averaged and irregularities on the screen can be reduced.

In this case, a technique similar to that explained in the firstembodiment of the present invention can be employed as the specificcontrol method. Alternatively, as already explained in the secondembodiment of the present invention, the signal whose pulses arerestricted by a number set as the phase control number may be generatedfrom the master clock signal, and the generated signal may be suppliedas a clock signal to the multi-phase control signal generating circuit93.

As mentioned above, according to the present invention, there isprovided a semiconductor integrated circuit which includes a pluralityof interleave-operating ADCs operated in parallel or an imaging ADC forsequentially switching between a plurality of circuit elements, andwherein, even when an image signal of any specification is input, theoutput signal of the imaging ADC can be averaged and irregularities onthe screen can be reduced. More in detail, even when outputs of theplurality of ADCs vary, the screen is re-displayed on the image displaydevice at a rate of several ten cycles per second. Thus, irregularitieson the screen can be averaged and can be seen regular to human eye.

As a result, even when an LSI having substantially the same level offluctuation as in the prior art is employed, the image quality of theimaging ADC can be increased only by a slight addition of circuit.Alternatively, since the influences of variations in the circuitelements can be reduced, the surface area of the circuit elements can bemade small compared with the prior art imaging ADC capable of outputtingan image having the same level of image quality. As a result, a straycapacitance can be decreased, which realizes high-speed operation.

INDUSTRIAL APPLICABILITY

The present invention can be applied to an image apparatus, a computeror the like which transmits image data and audio data.

1. A semiconductor integrated circuit comprising: a plurality ofanalog/digital converting circuits operated in parallel for sequentiallyconverting an analog image signal to a digital image signal; amulti-phase clock signal generating circuit for generating multi-phaseclock signals to be used for periodically operating said plurality ofanalog/digital converting circuits in a certain order; and a controlcircuit for controlling said multi-phase clock signal generating circuitto change at least one of a period and an order of operating saidplurality of analog/digital converting circuits in response to at leasta synchronization signal which corresponds to the analog image signal.2. A semiconductor integrated circuit comprising: a plurality ofanalog/digital converting circuits operated in parallel for sequentiallyconverting an analog image signal to a digital image signal; amulti-phase clock signal generating circuit for generating multi-phaseclock signals to be used for periodically operating said plurality ofanalog/digital converting circuits in a certain order; and a controlcircuit for controlling said multi-phase clock signal generating circuitto change at least one of a period and an order of operating saidplurality of analog/digital converting circuits, wherein said controlcircuit controls said multi-phase clock signal generating circuit basedon a number of pixels included in one frame of the digital image signaland a number of said plurality of analog/digital converting circuitssuch that said plurality of analog/digital converting circuits neverperforms conversion in a same period and in a same order with respect topixels for at least successive two frames.
 3. The semiconductorintegrated circuit according to claim 2, wherein said control circuitcontrols said multi-phase clock signal generating circuit based on thenumber of pixels included in one frame of the digital image signal andthe number of said plurality of analog/digital converting circuits suchthat said plurality of analog/digital converting circuits never performsconversion in a same period and in a same order with respect to pixelsfor successive N frames where the number of said plurality ofanalog/digital converting circuits is N.
 4. The semiconductor integratedcircuit according to claim 1, wherein said control circuit controls saidmulti-phase clock signal generating circuit based on an output of apseudorandom number generating circuit for generating at least Nintegers where the number of said plurality of analog/digital convertingcircuits is N so as to shift timing of sampling operation of saidplurality of analog/digital converting circuits.
 5. A semiconductorintegrated circuit comprising: a plurality of analog/digital convertingcircuits operated in parallel for sequentially converting an analogimage signal to a digital image signal; a multi-phase clock signalgenerating circuit for generating multi-phase clock signals to be usedfor periodically operating said plurality of analog/digital convertingcircuits in a certain order; and a control circuit for controlling saidmulti-phase clock signal generating circuit to change at least one of aperiod and an order of operating said plurality of analog/digitalconverting circuits, wherein said multi-phase clock signal generatingcircuit counts pulses of a master clock signal and stores counter valuesto be used for generating the multi-phase clock signals; and saidcontrol circuit controls said multi-phase clock signal generatingcircuit by changing the counter values stored in said multi-phase clocksignal generating circuit at predetermined timing.
 6. A semiconductorintegrated circuit comprising: a plurality of analog/digital convertingcircuits operated in parallel for sequentially converting an analogimage signal to a digital image signal; a multi-phase clock signalgenerating circuit for generating multi-phase clock signals to be usedfor periodically operating said plurality of analog/digital convertingcircuits in a certain order; and a control circuit for controlling saidmulti-phase clock signal generating circuit to change at least one of aperiod and an order of operating said plurality of analog/digitalconverting circuits, wherein said multi-phase clock signal generatingcircuit counts pulses of a master clock signal and stores counter valuesto be used for generating the multi-phase clock signals; and saidcontrol circuit controls said multi-phase clock signal generatingcircuit by changing the counter values stored in said multi-phase clocksignal generating circuit at predetermined timing based on a countervalue obtained by counting the pulses of the master clock signal.
 7. Asemiconductor integrated circuit comprising: a plurality ofanalog/digital converting circuits operated in parallel for sequentiallyconverting an analog image signal to a digital image signal; amulti-phase clock signal generating circuit for generating multi-phaseclock signals to be used for periodically operating said plurality ofanalog/digital converting circuits in a certain order; and a controlcircuit for controlling said multi-phase clock signal generating circuitto change at least one of a period and an order of operating saidplurality of analog/digital converting circuits, wherein said controlcircuit outputs a clock signal obtained by suppressing a predeterminednumber of pulses included in a master clock signal; and said multi-phaseclock signal generating circuit generates said multi-phase clock signalsbased on counter values obtained by counting pulses of the clock signaloutputted from said control circuit.
 8. The semiconductor integratedcircuit according to claim 7, wherein said control circuit outputs theclock signal obtained by suppressing the predetermined number of plusesincluded in the master clock signal in a blanking period of the digitalimage signal.
 9. A semiconductor integrated circuit comprising: ananalog/digital converting circuit for converting an analog image signalto a digital image signal by sequentially switching between a pluralityof circuit elements; a first control circuit for controlling saidanalog/digital converting circuit to periodically arrange said pluralityof circuit elements in a certain order; and a second control circuit forcontrolling said first control circuit to change at least one of aperiod and an order of arranging said plurality of circuit elements inresponse to at least a synchronization signal which corresponds to theanalog image signal.
 10. A semiconductor integrated circuit comprising:an analog/digital converting circuit for converting an analog imagesignal to a digital image signal by seciuentiallv switching between aplurality of circuit elements; a first control circuit for controllingsaid analog/digital converting circuit to periodically arrange saidplurality of circuit elements in a certain order; and a second controlcircuit for controlling said first control circuit to change at leastone of a period and an order of arranging said plurality of circuitelements, wherein said second control circuit controls said firstcontrol circuit based on a number of pixels included in one frame of thedigital image signal and a number of said plurality of circuit elementssuch that said analog/digital converting circuit never arranges saidplurality of circuit elements in a same period and in a same order withrespect to pixels for at least successive two frames.
 11. Asemiconductor integrated circuit comprising: an analog/digitalconverting circuit for converting an analog image signal to a digitalimage signal by sequentially switching between a plurality of circuitelements; a first control circuit for controlling said analog/digitalconverting circuit to periodically arrange said plurality of circuitelements in a certain order; and a second control circuit forcontrolling said first control circuit to change at least one of aperiod and an order of arranging said plurality of circuit elements,wherein said second control circuit controls said first control circuitbased on the number of pixels included in one frame of the digital imagesignal and the number of said plurality of circuit elements such thatsaid analog/digital converting circuit never arranges said plurality ofcircuit elements in the same period and in the same order with respectto pixels for successive N frames where a number of said circuitelements is N.
 12. A semiconductor integrated circuit comprising: ananalog/digital converting circuit for converting an analog image signalto a digital image signal by sequentially switching between a pluralityof circuit elements; a first control circuit for controlling saidanalog/digital converting circuit to periodically arrange said pluralityof circuit elements in a certain order; and a second control circuit forcontrolling said first control circuit to change at least one of aperiod and an order of arranging said plurality of circuit elements,wherein said first control circuit counts a master clock signal andstores counter values to be used for generating multi-phase controlsignals for controlling said analog/digital converting circuit; and saidsecond control circuit controls said first control circuit by changingthe counter values stored in said first control circuit at predeterminedtiming.
 13. A semiconductor integrated circuit comprising: ananalog/digital converting circuit for converting an analog image signalto a digital image signal by sequentially switching between a pluralityof circuit elements; a first control circuit for controlling saidanalog/digital converting circuit to periodically arrange said pluralityof circuit elements in a certain order; and a second control circuit forcontrolling said first control circuit to change at least one of aperiod and an order of arranging said plurality of circuit elements,wherein said first control circuit counts a master clock signal andstores counter values to be used for generating multi-phase controlsignals for controlling said analog/digital converting circuit; and saidsecond control circuit controls said first control circuit by changingthe counter values stored in said first control circuit at apredetermined interval based on a counter value obtained by counting amaster clock signal.
 14. A semiconductor integrated circuit comprising:an analog/digital converting circuit for converting an analog imagesignal to a digital image signal by sequentially switching between aplurality of circuit elements; a first control circuit for controllingsaid analog/digital converting circuit to periodically arrange saidplurality of circuit elements in a certain order; and a second controlcircuit for controlling said first control circuit to change at leastone of a period and an order of arranging said plurality of circuitelements, wherein said second control circuit outputs a clock signalobtained by suppressing a predetermined number of pulses included in amaster clock signal; and said first control circuit generatesmulti-phase control signals for controlling said analog/digitalconverting circuit based on counter values obtained by counting theclock signal outputted from said second control circuit.
 15. Thesemiconductor integrated circuit according to claim 13, wherein saidsecond control circuit outputs the clock signal obtained by suppressingthe predetermined number of pulses included in the master clock signalin a blanking period of the digital image signals.